52-GHz Millimetre-Wave PLL Synthesizer

Multiple 60-GHz WPAN (Wireless Personal Area Network) radio transceiver chips using CMOS or BiCMOS process have been developed as wireless communication service of several-gigabit rate [Reynolds, 2006] [Razavi, 2006]. In a 60GHz millimetre-wave transceiver, frequency synthesizer is a key building block. It is very difficult to design the PLL-based programmable synthesizer directly at 60GHz band without tripler or doubler. A 14.25-16GHz programmable PLL synthesizer was presented as a frequency source for 60GHz directconversion receiver. Its output frequencies of 28.5-32GHz are generated using Wilkinson power combiner [Lee, 2008]. A 16-18.8GHz programmable PLL was developed as a local oscillator for 60GHz dual-conversion super-heterodyne transceiver [Floyd, 2008]. Its tripled output frequency becomes 46 to 54GHz. Also, various non-programmable PLLs have been developed as millimetre-wave frequency sources, but they are not suitable for 60GHz WPAN radio covering 57 to 64GHz range [Winkler, 2005] [Lee, 2007]. In this chapter, we present a 52-GHz PLL-based synthesizer for 60GHz dual-conversion super-heterodyne receiver. The synthesizer is composed of 26GHz programmable PLL and 52GHz frequency doubler. The 26GHz PLL consists of PFD, charge pump, loop filter, LC VCO, and four-modulus divider. The synthesizer shows a 50-53GHz locking range, and generates two channels of 50.304GHz and 52.4GHz when 262MHz reference is used. The PLL achieves phase noises of – 89dBc/Hz from 26.2GHz and – 81dBc/Hz from 52.4GHz, at 1MHz offset frequency, respectively. The synthesizer represents spurious noise level of – 42dBc/Hz, and consumes 160mA at 2.5V. In section 2 of this chapter, a 60GHz dual-conversion super-heterodyne receiver is briefly introduced. In section 3, the 52GHz PLL synthesizer including frequency doubler is described in detail. The experimental results are presented in section 4, and finally, conclusion is drawn in section 5.